Comparative Study of Power Optimization Using Look Ahead Clock Gating Based on Auto Gated Flipflops
ثبت نشده
چکیده
Abstract:Gating of the clock signal in VLSI chips is nowadays a mainstream methodology for reducing switching power consumption.several techniques to reduce dynamic power of which clock gating is predominant.clock gating is employed at all levels:system architecture,block design,logic design and gates.three gating methods are known.the most popular is synthesis based on the logic of underlying system.It leaves the majority of clock pulses driving flipflops redundant.The data driven clock gating yields higher power savings but its design methodology is complex.Third method is auto gated flipflops,it is simple but yields small power savings. Our data-driven clock gating is integrated into an Electronic Design Automation (EDA) commercial backend design flow, achieving total power reduction of 15%–20% for various types of large-scale state-of-the-art industrial and academic designs in 40 and 65 manometer process technologies.
منابع مشابه
Comparative analysis of Clock gated Data Look Ahead and Conditional Capture Flip-Flops and their area of Applications
Flip-Flops are off many types. Choosing the correct type FF for any application is very important to achieve high performance. the data look ahead d Flip-Flop (DLDFF) from the family of master-slave type is compared with pulse triggered conditional capture Flip-Flop(CCFF).The effect of clock gating on the performance of these Flip-Flops are analyzed. The two Flip-Flops are compared, with clock ...
متن کاملIntegration of Bus Specific Clock Gating and Power Gating
In integrated circuits a gargantuan portion of chip power is mostly consumed by clocking systems which comprises of flipflops, latches and clock distribution networks. The two most widely used techniques for the reduction of dynamic and leakage power are clock gating (CG) and power gating (PG). The two techniques CG and PG are coupled in such a way that the clock enable signal is generated by C...
متن کاملLow Dropout Based Noise Minimization of Active Mode Power Gated Circuit
Power gating technique reduces leakage power in the circuit. However, power gating leads to large voltage fluctuation on the power rail during power gating mode to active mode due to the package inductance in the Printed Circuit Board. This voltage fluctuation may cause unwanted transitions in neighboring circuits. In this work, a power gating architecture is developed for minimizing power in a...
متن کاملEasy and difficult exact covering problems arising in VLSI power reduction by clock gating
Several graph matching and exact covering problems arising in VLSI low-power design optimization by clock gating are presented. To maximize the power savings, clock gating requires optimal grouping of Flip-Flops (FFs), which depends on FFs’ data toggling correlations and probabilities. These naturally lead to optimal matching and exact covering problems. We present three problems arising by dif...
متن کاملPower reduction on clock-tree using Energy recovery and clock gating technique
Power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. Hence, low power clocking schemes are promising approaches for low-power design. We propose four novel energy recovery clocked flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. Th...
متن کامل